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- Subject: RE: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor
- From: "Solinsky, Jeff - PAL" <Jeff.Solinsky@...>
- Date: Tue, 31 Jan 2012 18:02:42 -0500
I'm replying to my last post here...
Solinsky, Jeff - Wrote:
> Tomorrow I will set the options to enable the _dl_if_debug_dprint() and
> sprinkle a bit of that to see what is going wrong. I'm thinking more info
> is needed to make a good guess as to what is going wrong, as one of the
> addresses could have been clobbered; I wonder if the problem might still
> be related to the cache sync function in the kernel.
The crash is occurring when unmapping linux-vdso32.so.1, which is a decent indication that maybe I did something wrong in __kernel_sync_dicache() when I added the code that also invalidates the instruction cache instead of only the data cache? Or perhaps anything that links linux-vdso32.so.1 is crashing on exit regardless of whether __kernel_sync_dicache() is executed, I'll have to check that tomorrow also.
The output now when the crash occurs when LuaJIT 2 exits:
calling FINI: /lib/libdl.so.0
do_dlclose():522: /lib/linux-vdso32.so.1: usage count: 1
do_dlclose():547: unmapping: /lib/linux-vdso32.so.1
Segmentation fault
So I expect the crash is in this code:
_dl_if_debug_print("unmapping: %s\n", tpnt->libname);
end = 0;
for (i = 0, ppnt = tpnt->ppnt;
i < tpnt->n_phent; ppnt++, i++) {
if (ppnt->p_type != PT_LOAD)
continue;
if (end < ppnt->p_vaddr + ppnt->p_memsz)
end = ppnt->p_vaddr + ppnt->p_memsz;
}
_dl_munmap((void*)tpnt->loadaddr, end);
/* Free elements in RTLD_LOCAL scope list */
for (runp = tpnt->rtld_local; runp; runp = tmp) {
tmp = runp->next;
free(runp);
}
Tomorrow, I will see more exactly where in this code it is dying.
> Would it do any good to post the powerpc assembly code I'm using to
> implement __kernel_sync_dicache()? It's basically a merge of what linux
> 2.6.29 was doing into the 2.6.20 kernel source we are using.
V_FUNCTION_BEGIN(__kernel_sync_dicache)
.cfi_startproc
mr r11,r3
li r7,32
addi r5,r7,-1
andc r6,r3,r5 /* round low to line bdy */
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
srwi. r8,r8,5 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
1: dcbst 0,r6
add r6,r6,r7
bdnz 1b
sync
/* Now invalidate the instruction cache */
li r7,32
addi r5,r7,-1
andc r6,r11,r5 /* round low to line bdy */
subf r8,r6,r4 /* compute length */
add r8,r8,r5
li r9,5
srw. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
2: icbi 0,r6
add r6,r6,r7
bdnz 2b
isync
li r3,0
blr
.cfi_endproc
V_FUNCTION_END(__kernel_sync_dicache)
Any help is much appreciated. I'm so close to working LuaJIT 2 on MPC8248.
~ Jeff
- References:
- LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Solinsky, Jeff - PAL
- Re: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Mike Pall
- RE: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Solinsky, Jeff - PAL
- RE: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Solinsky, Jeff - PAL
- RE: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Solinsky, Jeff - PAL
- Re: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Mike Pall
- RE: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Solinsky, Jeff - PAL
- RE: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Solinsky, Jeff - PAL
- Re: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Mike Pall
- RE: LuaJIT 2.0 beta 9 on PPC GCC 4.4.6 uClibc 0.9.29 mpc8248 PowerQuicc II processor, Solinsky, Jeff - PAL