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On Tue, 23 Nov 2010 12:39:02 +0100, Gilles Ganault
<> wrote:
>Where is this variable defined, then?

Apparently, when "make" finds an undefined variable, it uses it as-is,
turns it into lower-case, and gives it a go.

So since "$(MAKE)" is not defined in the Makefile, make will use MAKE,
turn it into "make", and just call the "make" binary.

Sorry about asking in this mailing list, since it's really a
"make"-related question.