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- Subject: Re: [PATCH] Fast String Hash
- From: KHMan <keinhong@...>
- Date: Tue, 18 Dec 2007 10:33:21 +0800
David Olofson wrote:
> On Monday 17 December 2007, Mike Pall wrote:
> [snip snip]
> Could probably be config/compile time detected and used only on
> platforms that need it. Unfortunately though, there are CPU families
> where older ones can't do unaligned access, whereas newer ones can;
> for example MC68000..20 vs MC60030, but well... I guess you'd just
> compile for the most restricted CPUs your code will be used on - just
> as it is with the x86 family and SIMD extensions and whatnot.
> BTW, have you considered the penalty of unaligned access in this
> context? (Don't even know if it's significant on modern x86 in
> situations like this...)
As far as manufacturers' claims go...
AMD #25112 PDF p. 111 says a minimum 1-cycle penalty for unaligned
access, more for 64-bit.
Intel #248966 PDF p. 122 doesn't say anything specific about
penalty, only the usual recommendation, but it does have a big
warning about accesses across cache lines.
I can't find any micro benchmark that checks for unaligned access
penalty. lmbench development seems more focused on cache and cores.
Well, it's only 2 unaligned accesses... Still, it would be
interesting and useful to quantify unaligned access behaviour, and
analyze and optimize the snippet.
Kein-Hong Man (esq.)
Kuala Lumpur, Malaysia