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This is probably a rather naive question. Apologies if
it has come up before. Lots of CPU instruction sets
have LOADQ, ADDQ, SUBQ instructions that load/add/subtract
small constants encoded as part of the instruction
itself. I was slightly surprised to see that the Lua 5
VM instruction set did not have any, but that all
constants were fetched from a constants pool. Although
this makes for conceptual simplicity it means that
all constant loading involves memory fetches. On a
CPU architecture like the ARM, and I guess on any
RISC design, efficiency means minimising memory fetches.
There seems to be plenty of space for Q-versions of
some of the Lua VM opcodes, and it would not be hard
to extend the parser to recognize the small number literals
that should invoke them. Has anybody done this, or is it
reckoned that the effort is not worth the likely gains?

Gavin Wraith (
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